Estimating worst-case latency of on-chip interconnects with formal simulation

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Publication year
2017
Author(s)
Verbeek, F.
Vugt, N. van
Publisher
New York : ACM;IEEE
ISBN
9780983567875
In
Stewart, D. (ed.), FMCAD 17 :Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) TU Wien, Vienna, Austria, October 2-6, 2017, pp. 204-211
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Annotation
FMCAD :17th Conference on Formal Methods in Computer-Aided Design (FMCAD 2017) TU Wien, Vienna, Austria, October 2-6, 2017
Publication type
Article in monograph or in proceedings
Please use this identifier to cite or link to this item: https://hdl.handle.net/2066/178783   https://hdl.handle.net/2066/178783
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